Package: golang.org/x/sys/cpu

package cpu Import Path golang.org/x/sys/cpu (on go.dev) Dependency Relation imports 5 packages, and imported by 3 packages

Involved Source Files byteorder.go d cpu.go Package cpu implements processor feature detection for various CPU architectures. cpu_gc_x86.go cpu_linux_noinit.go cpu_x86.go endian_little.go hwcap_linux.go parse.go runtime_auxv.go runtime_auxv_go121.go cpu_x86.s

Package-Level Type Names (total 5, in which 1 is exported)

/* sort exporteds by: alphabet | popularity */

type CacheLinePad (struct) CacheLinePad is used to pad structs to avoid false sharing.

/* 4 unexporteds ... *//* 4 unexporteds: */

type bigEndian (struct) Methods (total 2, both are exported) ( bigEndian) Uint32(b []byte) uint32 ( bigEndian) Uint64(b []byte) uint64 Implements (at least 2, neither is exported) /* 2+ unexporteds ... *//* 2+ unexporteds: */ bigEndian : byteOrder bigEndian : vendor/golang.org/x/sys/cpu.byteOrder

type byteOrder (interface) byteOrder is a subset of encoding/binary.ByteOrder. Methods (total 2, both are exported) ( byteOrder) Uint32([]byte) uint32 ( byteOrder) Uint64([]byte) uint64 Implemented By (at least 9, in which 1 is exported) encoding/binary.ByteOrder (interface) /* 8+ unexporteds ... *//* 8+ unexporteds: */ bigEndian littleEndian encoding/binary.bigEndian encoding/binary.littleEndian encoding/binary.nativeEndian vendor/golang.org/x/sys/cpu.bigEndian vendor/golang.org/x/sys/cpu.byteOrder (interface) vendor/golang.org/x/sys/cpu.littleEndian Implements (at least one unexported) /* at least one unexported ... *//* at least one unexported: */ byteOrder : vendor/golang.org/x/sys/cpu.byteOrder As Outputs Of (at least one unexported) /* at least one unexported ... *//* at least one unexported: */ func hostByteOrder() byteOrder

type littleEndian (struct) Methods (total 2, both are exported) ( littleEndian) Uint32(b []byte) uint32 ( littleEndian) Uint64(b []byte) uint64 Implements (at least 2, neither is exported) /* 2+ unexporteds ... *//* 2+ unexporteds: */ littleEndian : byteOrder littleEndian : vendor/golang.org/x/sys/cpu.byteOrder

type option (struct) Option names should be lower case. e.g. avx instead of AVX. Fields (total 5, all are exported) Enable bool // whether feature should be enabled Feature *bool Name string Required bool // whether feature is mandatory and can not be disabled Specified bool // whether feature value was specified in GODEBUG

Package-Level Functions (total 14, none are exported) /* 14 unexporteds ... *//* 14 unexporteds: */

func archInit()

func cpuid(eaxArg, ecxArg uint32) (eax, ebx, ecx, edx uint32) cpuid is implemented in cpu_x86.s for gc compiler and in cpu_gccgo.c for gccgo.

func doinit()

func getAuxv() []uintptr

func hostByteOrder() byteOrder hostByteOrder returns littleEndian on little-endian machines and bigEndian on big-endian machines.

func init()

func initOptions()

func isSet(bitpos uint, value uint32) bool

func parseRelease(rel string) (major, minor, patch int, ok bool) parseRelease parses a dot-separated version number. It follows the semver syntax, but allows the minor and patch versions to be elided. This is a copy of the Go runtime's parseRelease from https://golang.org/cl/209597.

func processOptions()

func readHWCAP() error

func runtime_getAuxv() []uintptr

func xgetbv() (eax, edx uint32) xgetbv with ecx = 0 is implemented in cpu_x86.s for gc compiler and in cpu_gccgo.c for gccgo.

Package-Level Variables (total 11, in which 7 are exported)

var ARM struct{_ CacheLinePad; HasSWP bool; HasHALF bool; HasTHUMB bool; Has26BIT bool; HasFASTMUL bool; HasFPA bool; HasVFP bool; HasEDSP bool; HasJAVA bool; HasIWMMXT bool; HasCRUNCH bool; HasTHUMBEE bool; HasNEON bool; HasVFPv3 bool; HasVFPv3D16 bool; HasTLS bool; HasVFPv4 bool; HasIDIVA bool; HasIDIVT bool; HasVFPD32 bool; HasLPAE bool; HasEVTSTRM bool; HasAES bool; HasPMULL bool; HasSHA1 bool; HasSHA2 bool; HasCRC32 bool; _ CacheLinePad} ARM contains the supported CPU features of the current ARM (32-bit) platform. All feature flags are false if: 1. the current platform is not arm, or 2. the current operating system is not Linux.

var ARM64 struct{_ CacheLinePad; HasFP bool; HasASIMD bool; HasEVTSTRM bool; HasAES bool; HasPMULL bool; HasSHA1 bool; HasSHA2 bool; HasCRC32 bool; HasATOMICS bool; HasFPHP bool; HasASIMDHP bool; HasCPUID bool; HasASIMDRDM bool; HasJSCVT bool; HasFCMA bool; HasLRCPC bool; HasDCPOP bool; HasSHA3 bool; HasSM3 bool; HasSM4 bool; HasASIMDDP bool; HasSHA512 bool; HasSVE bool; HasASIMDFHM bool; _ CacheLinePad} ARM64 contains the supported CPU features of the current ARMv8(aarch64) platform. If the current platform is not arm64 then all feature flags are false.

var Initialized bool Initialized reports whether the CPU features were initialized. For some GOOS/GOARCH combinations initialization of the CPU features depends on reading an operating specific file, e.g. /proc/self/auxv on linux/arm Initialized will report false if reading the file fails.

var MIPS64X struct{_ CacheLinePad; HasMSA bool; _ CacheLinePad} MIPS64X contains the supported CPU features of the current mips64/mips64le platforms. If the current platform is not mips64/mips64le or the current operating system is not Linux then all feature flags are false.

var PPC64 struct{_ CacheLinePad; HasDARN bool; HasSCV bool; IsPOWER8 bool; IsPOWER9 bool; _ CacheLinePad} PPC64 contains the supported CPU features of the current ppc64/ppc64le platforms. If the current platform is not ppc64/ppc64le then all feature flags are false. For ppc64/ppc64le, it is safe to check only for ISA level starting on ISA v3.00, since there are no optional categories. There are some exceptions that also require kernel support to work (DARN, SCV), so there are feature bits for those as well. The struct is padded to avoid false sharing.

var S390X struct{_ CacheLinePad; HasZARCH bool; HasSTFLE bool; HasLDISP bool; HasEIMM bool; HasDFP bool; HasETF3EH bool; HasMSA bool; HasAES bool; HasAESCBC bool; HasAESCTR bool; HasAESGCM bool; HasGHASH bool; HasSHA1 bool; HasSHA256 bool; HasSHA512 bool; HasSHA3 bool; HasVX bool; HasVXE bool; _ CacheLinePad} S390X contains the supported CPU features of the current IBM Z (s390x) platform. If the current platform is not IBM Z then all feature flags are false. S390X is padded to avoid false sharing. Further HasVX is only set if the OS supports vector registers in addition to the STFLE feature bit being set.

var X86 struct{_ CacheLinePad; HasAES bool; HasADX bool; HasAVX bool; HasAVX2 bool; HasAVX512 bool; HasAVX512F bool; HasAVX512CD bool; HasAVX512ER bool; HasAVX512PF bool; HasAVX512VL bool; HasAVX512BW bool; HasAVX512DQ bool; HasAVX512IFMA bool; HasAVX512VBMI bool; HasAVX5124VNNIW bool; HasAVX5124FMAPS bool; HasAVX512VPOPCNTDQ bool; HasAVX512VPCLMULQDQ bool; HasAVX512VNNI bool; HasAVX512GFNI bool; HasAVX512VAES bool; HasAVX512VBMI2 bool; HasAVX512BITALG bool; HasAVX512BF16 bool; HasAMXTile bool; HasAMXInt8 bool; HasAMXBF16 bool; HasBMI1 bool; HasBMI2 bool; HasCX16 bool; HasERMS bool; HasFMA bool; HasOSXSAVE bool; HasPCLMULQDQ bool; HasPOPCNT bool; HasRDRAND bool; HasRDSEED bool; HasSSE2 bool; HasSSE3 bool; HasSSSE3 bool; HasSSE41 bool; HasSSE42 bool; _ CacheLinePad} X86 contains the supported CPU features of the current X86/AMD64 platform. If the current platform is not X86/AMD64 then all feature flags are false. X86 is padded to avoid false sharing. Further the HasAVX and HasAVX2 are only set if the OS supports XMM and YMM registers in addition to the CPUID feature bit being set.

/* 4 unexporteds ... *//* 4 unexporteds: */

var getAuxvFn () []uintptr getAuxvFn is non-nil on Go 1.21+ (via runtime_auxv_go121.go init) on platforms that use auxv.

var hwCap uint For those platforms don't have a 'cpuid' equivalent we use HWCAP/HWCAP2 These are initialized in cpu_$GOARCH.go and should not be changed after they are initialized.

var hwCap2 uint

var options []option options contains the cpu debug options that can be used in GODEBUG. Options are arch dependent and are added by the arch specific initOptions functions. Features that are mandatory for the specific GOARCH should have the Required field set (e.g. SSE2 on amd64).

Package-Level Constants (total 6, in which 1 is exported)

const IsBigEndian = false IsBigEndian records whether the GOARCH's byte order is big endian.

/* 5 unexporteds ... *//* 5 unexporteds: */

const _AT_HWCAP = 16

const _AT_HWCAP2 = 26

const cacheLineSize = 64

const procAuxv = "/proc/self/auxv"

const uintSize int = 64